This invention relates to a bucket-brigade delay line and more particularly deals with the problem which arises when delay lines for analogous signals composed of individual stages in accordance with the bucket-brigade delay line or the charge-coupled delay line principle are operated at a variable clock frequency.
Bucket brigade delay lines are known, for example, from "IEEE Journal of Solid-State Circuits," June 1969, pp. 131 to 136 and consist of a plurality of stages of the same kind each comprising a transistor and a capacitor arranged between the gate and the collector electrode thereof, and which are series-connected in such a way that the collector electrode of one transistor is connected to the emitter electrode of the next successive transistor. In such arrangements the gates of the even-numbered transistors are controlled by a first square-wave clock signal, and the gates of the odd-numbered transistors are controlled by a second square-wave clock signal of equal frequency, with the effective pulses thereof lying in the intervals between the effective pulses of the first clock signal.
Bucket brigade delay lines can be realized either with the aid of bipolar monolithic integrated circuits or with the aid of monolithic integrated insulated-gate field-effect transistor circuits.
Delay lines operating on the charge-coupled principle are known, for example, from the "Bell System Technical Journal," April 1970, pp. 587 to 600. The difference between bucket brigade delay lines and delay lines operating on the charge-coupled principle resides in that the diffusion zones existing in bucket-brigade delay lines, the capacitors and the emitter and collector zones are omitted. The delay line thus exclusively consists of closely adjacent channel zones controlled by the gate electrodes, which are coupled to one another by overlapping of the potential wells. Both the charge transfer and the charge storage are taken over exclusively by minority carriers.
In the course of this the semiconductor suface below the electrodes is in the so-called deep depletion mode. By means of a third clock signal, care is taken that potential barriers will result between three neighboring electrodes in the semiconductor body for taking over the charge storage as effected in the capacitors in the case of bucket-brigade circuits.
The problem referred to hereinbefore, as arising in such types of delay lines, resides in that during operation at a variable clock frequency, an unwanted component of that particular frequency will appear in the delayed analog output signal, by which the clock frequency is changed, hence modulated. This unwanted modulation is due to a clock frequency dependent modulation for which there may be a variety of causes depending on the operating conditions.
Thus, this unwanted modulation may result in cases where the phase position of the clock signals is dependent upon the clock frequency and where simultaneously there occurs an overlapping of the edges of the pulses or an overshooting of the clock signals. By providing for an exact clock signal treatment it is possible, however, to avoid this cause to a considerable extent even though not completely.
Secondly, the clock frequency dependent residual charge remaining in the capacitor of each stage subsequently to the charge reversal thereof, is considered as a further unavoidable cause of unwanted modulations, especially in the case of higher clock frequencies.
Thirdly, in the case of lower clock frequencies and higher temperatures, it is likewise unavoidable that an unwanted modulation becomes noticeable by the drifting of the d.c. level from stage to stage owing to a charge transfer via inverse currents. Fourthly and finally, in the case of delay lines which have been realized with the aid of monolithic integrated insulated-gate field-effect transistors, hence with the aid of the so-called MOS-technique, surface states below the oxide layer of the gate electrode of the transistors, because thay are charged during their turn-on phase and more or less completely discharged during their turn-off phase, lead to cumulative (i.e., number-of-stage-dependent) level drift which is dependent upon the frequency and which takes place in a direction opposite to that of the aforementioned inverse current dependent drift.
From the "IEEE Journal of Solid-State Circuits," April 1973, pp. 157 to 168, especially page 157, FIG. 2, it is known to solve the problem of compensating such unwanted modulations, in that a second delay line with an equal number of stages is connected in parallel with the delay line subjected to the unwanted modulation, with the signal each time being inverted before the input and after the output of one of the two lines, with the compensated signal finally being obtained by way of addition.
This solution to the aforementioned problem, however, is very costly and thus also involves a great surface requirement of the corresponding integrated circuit.